6.3.1. Slice Logic Interface: Clock and Data Signals

The signals in Table 6 shall constitute the data and clocks in the logic interface of the PHY. N is the ratio of the chip-to-chip per-wire data rate to the logic interface per-wire data rate.

6.4. Slice Logic (Link Layer) Interface for a Bidirectional PHY

6.5. Slice Logic (Link Layer) Interface aspects common to unidirectional and bidirectional PHYs

6.5.1. Slice Logic Interface: Control Signals

A BoW interface slice must provide the control and status signals shown in Table 7.

6.5.1.1. PHYResetB TX and RX

The PHYResetB pin shall be asserted by the link controller to initialize the PHY. While the PHYResetB signal is asserted, the PHY shall stay in its reset state. When the PHYResetB signal is de-asserted, the PHY shall perform any necessary self-alignment. The reset states are otherwise implementation-dependent and shall be documented in the datasheet of a particular implementation.

6.5.1.2. PHYReady TX

On a TX slice, the PHY shall assert PHYReady to indicate it is transmitting appropriate CLK and PCLK signals, and that it is ready to transmit data.

6.5.1.3. PHYReady RX

On an RX slice, when PHYResetB is deasserted, the PHY assumes that the corresponding TX slice is sending CLK and that the TX Link Layer is sending training data on the data wires.

After the RX slice clock self-alignments are complete, each RX PHY slice shall assert its PHYReady pin. How an RX PHY slice determines completion of the self-alignment is implementation-dependent. For instance, it may be determined by observing the settling of the DLL or by a simple timer. PHYReady asserted indicates that any data received will be captured correctly.

6.5.1.4. PHYIdle TX

Further description of this optional signal and its functionality are provided in Section 11.

6.5.2. Programming

There shall be an AMBA APB programming interface to control internal registers for control and status readout of the PHY.

The internal registers are implementation-dependent. The internal registers shall be fully documented in the PHY datasheet.

6.5.3. Link Controller

There shall be a Link Controller (LC) outside the PHY. This will manage initialization of the Link. It may reside on one of the chiplets of the link, in a third chiplet in the package or outside the package.

Communication from the Link Controller across chiplets shall be by a transport mechanism outside the BoW link. This could be a serial link like SPI or I2C, but this is not specified at this time.

Link initialization is described in Section 14. Clocks are described in 10.2.

7. BoW Modes and Reach

A BoW PHY slice must conform to at least one of the BoW Modes seen in Table 3. The recommended maximum wire reach for different packaging types and terminations is seen in Table 8. Exceeding these reach values may degrade the voltage margins at the receiver. See section 12 for how TX, RX and channels are qualified.

“Laminate” is intended to include organic laminate packages (a.k.a. “buildup”") and similar technologies with approximately 25 μm line and space rules. The minimum wire length for closely spaced chips in these technologies is around 3 mm for the slice closest to the chip edge.

“Advanced” is intended to include silicon interposer and similar technologies. These have much finer line and space dimensions, but traces are usually much more resistive than in organic laminate packages and will be limited to much shorter trace lengths. Due to these short traces, termination is not expected to be useful for implementations targeting Advanced packaging. The minimum wire length in these technologies may be less than 1 mm.

Adding termination increases the speed and/or reach, at the expense of greater design complexity and power.

8. BoW Physical Configuration

8.1. Dead-Bug Views

The physical diagrams and descriptions in this document must be interpreted as looking down at the top layer of the unpackaged chiplets. Since these are flip-chip packages, these views are equivalent to looking through the bottom of the package with the balls up (dead bug view). For the view as seen looking down on a package as mounted on a PCB (live bug view), these views must be mirrored.

8.2. BoW Components

A BoW link between two chiplets is made up of wires, slices, and stacks as seen in Figure 5.

• The signal traces in the package between chiplets are called wires.
• A slice is the the basic unit of a BoW PHY. It must have 18 or 20 signal bumps. It must have 2 bumps for the differential clock and 16 single-ended data bumps. It may also have the optional single-ended signals AUX and FEC. The long edge of a slice must be parallel to the chip edge.
• A stack is composed of one or more slices stacked from the chip edge towards the center. The slice positions are designated A, B, C, etc, starting with the slice closest to the edge of the chip.
• A link from one chiplet to another is composed of one or more stacks placed along the chip edge. A link may be configured with equal numbers of RX and TX slices, or it may be asymmetric or one-way.

8.3. Example Link

The minimal bidirectional reference link is shown in Figure 6.

In this example, each chiplet has one TX slice and one RX slice, arranged in two one-slice stacks on each chiplet. This is a dead-bug view.

8.4. BoW Half-Link Components

For low-bandwidth or constrained die-edge applications a half-link or 8-bit link consisting of 8 data wires per half-slice is defined as shown in Figure 7.

• A half-slice is a smaller version of a slice with 10 or 12 signal bumps. It must have 10 or 12 signal bumps. It must have 2 bumps for the differential clock and 8 single-ended data bumps. It may also have the optional single-ended signals AUX and FEC.
• A half-stack is composed of one or more half-slices stacked from the chip edge towards the center. It may not contain a mix of half-width and regular-width slices. The slice positions are designated A, B, C, etc, starting with the slice closest to the edge of the chip.
• A half-link from one chiplet to another is composed of one or two half-stacks placed along the chip edge. A half-link may not contain more than two half-stacks at which point the use of regular-width slices is recommended A half-link may be configured with equal numbers of RX and TX slices, or it may be asymmetric or one-way.

8.4.1. Minimal Half-Link

The minimal bidirectional reference half-link is shown in Figure 8 .

In this example, each chiplet has one TX half-slice and one RX half-slice, arranged in two half-slice stacks on each chiplet. This is a dead-bug view.

8.4.2. Half-Link to Regular Link Interoperability

A half-link shall be compatible with a regular-width link by fanning out the signal wires D0-D7, the differential clock pins and optionally AUX and FEC, see Figure 9 . Each half-slice shall be connected to a unique regular-width slice on the other chiplet. Connecting two half-slices on one chiplet to a regular slice on another chiplet is not permitted.

To accommodate this compatibility, the intended configuration (8-bit or 16-bit slices) shall be programmed into the PHY at startup via APB. Unused transmit pins should be open-circuited to save power, and unused receive pins should be disabled or make use of a weak pulldown (as discussed in Section 9.2).

8.5. Die-to-Die Signals

Each BoW slice consists of a differential clock pair, 16 single-ended data wires, and optional wires FEC and AUX. Each BoW slice is unidirectional when in operation. A PHY may be designed as RX-only and TX-only slices, or each slice may have both TX and RX capability, one of which is selected at configuration time. A bidirectional link is composed of some whole number of slices configured for RX and some whole number of slices for TX.

FEC (Forward Error Correction) is an optional signal that allows using error correction to improve the bit error rate (BER). AUX is an optional signal that may be used for purposes such as DBI, flow control, redundancy, etc. Chiplets A and B will need to agree on the details on FEC and AUX usage, which is defined in the Link Layer.

8.6. Signal Ordering

A BoW interface must conform to these wire order rules at the edge of the chip:

• The signals for a TX slice or a bidirectional slice are in the following order at the chip edge, going clockwise around the chiplet in a dead-bug view: AUX, D0, D1, D2, D3, D4, D5, D6, D7, CLK+, CLK-, D8, D9, D10, D11, D12, D13, D14, D15, FEC
• The signals for an RX slice are in the reversed order (ascending goes counter-clockwise)
• The same clockwise/counter-clockwise ordering is used on all four sides of a chiplet
• The AUX and FEC signals may be omitted
• For a half-slice D8, D9, D10, D11, D12, D13, D14, D15 shall be omitted

8.7. Bump Arrangements

Note that bump patterns are not specified by BoW; only the signal ordering at the chip edge is specified for interoperability.

The reference example in Figure 6 uses hexagonal closest packing for the bumps: two rows for signal bumps and one row for power and ground bumps. In this pattern, the wire pitch is half the bump pitch.

8.7.1. Alternate Bump Arrangements

Alternate bump arrangements may include:

• 90-degree rotation of the hexagonal packing direction (to decrease the wire pitch 14%)
• square bump arrays instead of hexagonal (for regularity of layout)
• more than two rows of signal bumps (to decrease the wire pitch without changing the bump pitch)
• different ordering of power and ground bumps
• multiple power and ground rows

Somewhat different wire pitches between two chiplets may be accommodated with fan-out in the chip-to-chip wires. This is limited by the maximum skew due to different wire lengths - see section 12.1.

8.8. Cross Section

An example cross section for an organic laminate (a.k.a. “buildup”) package is shown in Figure 10.

In an organic laminate package, signal layers should be alternated with ground layers in order to maintain a controlled impedance of 50 Ω. Each slice position (A, B, C, D) should be associated with one signal layer and there should be no mixing of signals from multiple slices.

In any technology, the position-A slice on chiplet A must be connected to the position-A slice on chiplet B (one must be configured for TX and one for RX). The position-B slices are connected together, and so on.

There is no specified limit to the number of slices in a stack. In organic laminate, the practical limit in 2020 is an 8-2-8 laminate which supports 4 slices as shown in Figure 10. A 7-2-7 laminate may support 4 slices by omitting the top GND layer, but with reduced signal integrity. Layers on the bottom side of the package typically cannot be used for BoW signals due to low via density passing through the thick central core layer.

In advanced packaging technologies, the shorter wire lengths and higher wire resistance suggests the use of non-controlled-impedance wires and unterminated transmitters and receivers. The smaller wire and space dimensions may allow the wires for multiple slices to be interleaved on a single wiring layer. The wire order within each slice must be maintained, even if interleaving with other slices is used.

8.9. Staggered Slices

To optimize the density of hexagonal bump arrays, slices in positions B and D may be offset horizontally by one half the bump pitch as seen in Figure 11. This necessitates a one-bump-pitch horizontal jog in the wires for slices B and D. The practical effect of this 130-um jog across a 2.5+ mm wire between chiplets is very small.

An alternative arrangement is to keep the slices aligned vertically. This requires adding a small extra vertical space between the slices, for an overall increase of 4% of the slice area.

8.10. Slice Numbering

A BoW interface composed of unidirectional slices must conform to these slice numbering rules:

• The TX slices in a link are numbered from 0 at the upper left edge of the link (facing from the chip center to the edge in a dead-bug view) and ascending through the TX slices in a stack, then from stack to stack clockwise.
• The RX slices in a link are numbered from 0 at the upper right, through the RX slices in a stack, then stack to stack counterclockwise.

An example of this numbering is shown in Figure 12.

The signal ordering and slice numbering rules allow BoW chiplets to be connected without signal reordering regardless of chiplet rotations.

8.11. Slice Stacking Pattern for Symmetric Links

For bidirectional links, a pattern of alternating TX and RX stacks should be used. Figure 12 shows an example bidirectional link with 4 stacks of 4 slices each, for 8 TX and 8 RX slices on each chiplet. The first TX stack should be at the left edge of the link.

Asymmetric and unidirectional links may use any slice pattern, but the slice numbering rules must be observed.

In BoW-256 at 16 Gbps/wire, the link in Figure 12 provides a total of 2.0 Tb/s in each direction. In an organic substrate using the hexagonal bump pattern of Figure 6 with a bump pitch is 130 um, the total edge width is 5.2 mm (4.16 mm without AUX and FEC); the depth from the edge is 1.35 mm. In an interposer, if the bump pitch is 40 um, the edge width is 1.60 mm (or 1.28 mm) and the depth is 0.42 mm.

8.12. Connecting Bidirectional Slices

A bidirectional BoW PHY slice is designed to operate as RX or TX, to be configured upon powerup. This allows complete flexibility in link configuration and interoperability and also provides an opportunity for wafer-level loopback testing before package assembly (known good die).

In bidirectional slices, the wires and slices must be numbered as if they are all TX slices.

Bidirectional slices are connected from chiplet to chiplet as in Figure 13: AUX to FEC, D0 to D15, D1 to D14… FEC to AUX.

9. BoW PHY Electrical Specifications

In order to ensure interoperability between differing BoW PHY implementations, this chapter provides a set of electrical specifications that all such BoW PHY implementations must meet.

9.1. Voltages and Termination Resistance

All BoW implementations must support signaling based on a 0.75 V “I/O voltage”. BoW PHYs may also support higher or lower signaling voltages, but must support 0.75 V based signaling for interoperability.

Note that the simplest implementation is to provide a 0.75 supply voltage to the BoW VDD bumps, but the supply voltage may be different from the I/O voltage as long as the signal voltages meet the specification.

In doubly terminated modes of operation, the RX termination resistance must be connected to 0V, the I/O voltage, or mid-rail of the I/O voltage (e.g., 375 mV with a 0.75 V I/O voltage). The selection of termination voltage is expected to be static (hardwired) in the RX, and must be specified in the receiver's datasheet. It is expected that Source-Series-Terminated (SST) Transmitters will be largely agnostic to the choice of termination voltage on the receiver. Note that BoW receivers which support the optional data idle state described in Section 11.1 must terminate to 0V, and must not terminate to the I/O voltage or mid-rail.

Regardless of the value selected for the I/O supply voltage, BoW transmitters and receivers must meet the DC termination resistance requirements defined in Table 10. Note that TX/RX termination (output/input) resistance values are skewed low/high compared to the channel impedance in order to ensure that the DC single-ended voltage swing at the RX is never reduced to less than half of the I/O voltage (i.e., 375 mV for a 0.75 V I/O voltage). Note that these termination resistance values must be met with all combinations of data inputs (logical 1 and logical 0), termination voltage selections (ground terminated, supply terminated, or mid-rail terminated), and termination resistance values. For example, a BoW TX must achieve between 36 Ω and 50 Ω resistance when driving a load resistance (modeling the RX termination) of 50-69 Ω with any of the three termination options.

Especially in doubly terminated modes, within-slice variations of termination resistance would directly result in varying swing levels at each pin. Thus, in order to reduce or eliminate the need for per-pin voltage reference adjustment at the RX, Table 10 also specifies requirements on DC termination resistance matching across all I/O's within a given BoW slice. The σ for this variation in the table must be interpreted as capturing within-slice manufacturing variability across worst-case voltage/temperature operating conditions, and is expected to be primarily influenced by some combination of transistor and explicit resistor matching (with the mix depending on the circuit implementation).

9.2. PHY protection

The lifetime of a BoW PHY should not be negatively impacted (i.e., the PHY should not be damaged) despite exposure to the following conditions:

• The bumps are open-circuited, e.g., at wafer test, or if not connected in a package assembly.
• In the un-powered state when connected to a BoW PHY which may be powered or un-powered.
• In the reset state when connected to a BoW PHY which may be powered or un-powered.
• In a properly-configured operational state.

A BoW PHY implementation must document how long it can withstand without damage (i.e., without degradation in part lifetime) an accidental incorrect state with TX configured and enabled on both ends of a wire.

A bidirectional PHY slice shall have the TX circuits disabled (high impedance) upon assertion of PHYResetB and require an APB command to be turn them on.

A unidirectional PHY TX slice need not be disabled at reset.

All RX slices must avoid “crowbar” states where a floating or mid-range input voltage can cause a large DC current to flow in the RX circuit. Therefore a PHY must either:

• Turn off the RX circuits upon assertion of PHYResetB and require an APB command to be turn them on, or
• Include pulldown resistors on all bumps, including CLK+ and CLK- and ensure that all the RX circuits be in a low current state including the CLK RX circuit with both CLK+ and CLK- low.

9.3. ESD

BoW I/O shall be designed to withstand 50 V CDM (Charged Device Model) and 250 V HBM (Human Body Model) at the bumps. This requirement is deemed sufficient for intra-package signaling, similar to other die-to-die interface standards.

Note that for CDM, the ESD current corresponding to 50 V depends on the package size. (E.g., 50 V CDM on a 65 x 65 mm package is ~1.3 A.) A BoW PHY shall document the package size assumed for CDM.

9.4. Return Loss and Parasitic Capacitance

Since BoW PHYs are targeted for relatively dense and simple realizations, it is expected that the primary frequency-dependent parasitics seen at a PHY's I/Os will be capacitive in nature. Table 11 provides limits on the maximum “equivalent” capacitance allowed on each side of each BoW I/O pin. (E.g., a BoW-128 TX is allowed to have up to 500 fF of equivalent capacitance.) Note that while the maximum capacitance specification does increase at lower data-rates, it is recommended that BoW PHY implementations retain as low of a capacitance as practical in order to reduce power consumption and improve signal integrity.

Since the actual frequency-dependent impedance profile of any given implementation may be comprised of a complex electrical network, conformance with the “equivalent” capacitance metric is formally defined by requiring that the magnitude of the return loss of any BoW I/O must be lower than the maximum limits shown in Figures 14 and 15 below. (Note that the return loss requirements are different for TX and RX because of the differences in DC termination between the two sides.) Similarly to DC termination resistance, the maximum s₁₁ magnitude in the figure must be met with all combinations of data inputs (logical 1 and logical 0), termination voltage selections (ground terminated, supply terminated, or mid-rail terminated), and termination resistance values.

9.5. Receiver Bandwidth

While this specification does not place a direct requirement on the bandwidth of a BoW receiver implementation, such receivers should maintain an effective 3 dB bandwidth of at least (0.667/T_bit) Hz. For example, for a BoW-256 PHY, the receiver 3 dB bandwidth is recommended to be at least 10.667 GHz.

10. BoW PHY Timing Specifications

10.1. Bit Ordering

The PHY TX serializer shall order data this way (referring to Figure 16):

• On the first CLK edge (CLK+ rising) bits P_D[0:15] are sent on wires D[0:15]
• On the second CLK edge (CLK+ falling) bits P_D[16:31] are sent on wires D[0:15]
• and so on to bits P_D[M*16-16:M*16-1].
• Then the cycle repeats.

The RX PHY shall order bits in the same fashion. However, the bits at the RX PHY logic interface P_D[*] may be offset by a multiple of 16 bits from the TX order if the TX and RX PCLK dividers are not aligned. A PHY implementation may provide a way to align the TX and RX dividers, or it may rely on the Link Layer to rotate the RX P_D[*] bits to provide that alignment as part of the training of the Link Layer.

10.2. Clocking

Figure 16 shows the clock and data flow for a single TX slice and a single RX slice. On the TX side, data bits (and optional FEC and AUX bits) come in a wide word from the Link Layer, and are serialized to the line rate. At the RX side, they are sampled with a common slicer clock in most BoW implementations. BoW PHYs may optionally implement per-bit delay adjust or per-bit slicer clock adjust.

BoW PHYs shall be DDR (Double Data Rate) at the chip-to-chip interface: the data bit rate is twice the clock frequency, so data is clocked in on both edges of the clock in the RX slice. BoW PHYs shall be SDR (Single Data Rate) at the logic interface.

Table 12 provides recommended clock and data rates for each BoW mode. The ratio M should be limited to integers, preferably powers of two, and any other ratios should be implemented outside the PHY.

Note that higher PCLK rates (and lower M ratios) help reduce gate count and Link Layer latency, but lower rates are often more power efficient. The best PCLK rate(s) to implement for a particular chiplet will tend to be a function of its process node. For implementations in process nodes at 16 nm and below, supporting 1000 MHz is recommended.

Table 13 provides clock and data rates for an example with 4 Gbps wire data rate and M=4 to support a 1 Gbps data rate at the Link-PHY interface.

The DDR clock TxClk is provided to the TX PHY from elsewhere on Chiplet-A. This may come for example from an on-chip PLL (typically shared across multiple slices) or routed from the RxClk of an RX slice on Chiplet-A. In order to meet duty cycle requirements, a Duty Cycle Corrector (DCC) may be needed in the TX slice. TxClk is used to drive the serializers and provide the output CLK+, CLK- to Chiplet-B.

On the RX side, the PHY must align the slicer clock to sample the data correctly. This may be done with a DLL, adjustable delays, or other methods. If the PHY includes control logic to self-align the slicer clock for correct sampling of the data, the PHYReady signal must be asserted after the logic has determined that such alignment is complete. The RX PHY may output the received CLK as RxClk to the logic interface.

All BoW interfaces shall be source synchronous at the die-to-die interface within a slice. No modes of BoW require per-wire or per-slicer delay adjustments, but such capability may be optionally included.

Clock skew between the slices in each direction of a link likely depends on the implementation of the TxClk distribution to all the TX slices. That is, for the data flow from Chiplet A to Chiplet B, the TxClk distribution on Chiplet A probably dominates the the clock skew of the TX slices on Chiplet A and the clock skew of the RX slices on Chiplet B, and vice versa for flow from B to A. The skew between TX CLK signals within one direction of a link should be no more than 150 ps/stack along the chip edge. There is no specification of the skew between TxClk on Chiplet A vs. TxClk on Chiplet B nor between different links.

Note that the dividers creating PCLK in each PHY slice are not required to be aligned. This implies that they will tend to have random starting states, leading to additional PCLK misalignment between slices of up to one PCLK period. PHY implementations may optionally include methods to align these dividers.

On both the TX and RX sides, the Link Layer will usually need to include a Clock Domain Crossing (CDC) to align the data between CoreClk and PCLK. The Link Layer must be able to absorb the slice-to-slice clock skew and core clock distribution skew across a whole BoW link. Word alignment across a link need not be supported by the PHY; if required, it should be done in the Link Layer.

10.3. Clock and Data Specifications

In order to not introduce excess pessimism into the link budgets implied by the BoW specification and avoid unnecessary over-design of BoW PHY circuitry, note that both the TX and RX voltage and timing error component requirements account for deterministic (bounded) terms separately from random (unbounded) terms. However, in order to retain some degree of design flexibility on each of the TX and RX, a bound is always placed on the maximum deterministic error and on the maximum total error budget at the target error rate of 1e-15. Thus, if a given BoW PHY design achieves deterministic error performance better than that requirement set by the deterministic component, the random errors introduced by that design may be increased as long as the total error requirement at 1e-15 probability is still met.

Note that the error rate of 1e-15 is at the level of any individual wire within a slice. In other words, in a conformant BoW interface, no indvidual wire within the interface would have an error-rate exceeding 1e-15.

10.3.1. Transmitter Maximum Rise-Time

The maximum 20% - 80% rise-time at the output of BoW TX shall not exceed 23% of a UI. For example, for a BoW-128 transmitter, the 20% - 80% rise-time shall not exceed 28.75 ps. This rise-time shall be simulated with the TX (including all of its parasitics) driving an ideal load of 50 Ω (Z_chan).

10.3.2. Transmitter Differential Clock Timing Mismatch

The maximum timing mismatch between CLK+ and CLK- outputs at the TX shall not exceed 2.5% of a UI. For example, for a BoW-128 TX, the timing mismatch shall not exceed 3.125 ps.

10.3.3. Transmitter Correlated Jitter Filtering

For timing-error specifications provided in the following sections that are impacted by transmitter jitter, this jitter must be evaluated for CLK edges that are up to N_ck-d UI earlier than the CLK edge that launched the data bit being captured at the receiver. This is due to the fact that even though jitter on the data edges may be correlated with the CLK jitter, the slicer in the RX side is likely to use a different CLK edge due to delays in the RX-side clock alignment circuit (usually a DLL and clock distribution). See Section 10.3.7 for the receiver's requirements. For BoW-256 mode and lower rates, N_ck-d = 3 UI. For BoW-384 mode, N_ckd = 5 UI, and for BoW-512 mode, N_ck-d = 6 UI.

In order to properly account for the jitter filtering/peaking that will occur due to the difference in delay between the data launching edge at the TX and the data capturing edge at the RX, when evaluating the transmitter's jitter (and whether it meets the requirements described in this document), the jitter at the TX output that is correlated between the CLK and D lines shall be filtered by the following frequency-dependent transfer function:

where t_clk-d is the delay between the CLK edge that launched the data bit and the CLK edge used to capture it. Note that jitter that is not correlated between the CLK and D signals shall not be filtered by this transfer function. (I.e., if the CLK signal and a given D signal have completely independent sources of jitter added to them such as non-shared portions of the clock distribution network, those jitter sources shall not be filtered by H_{tx_jit}(jω). Since the total TX jitter after filtering by this transfer function might not be monotonic with t_clk-d, and since receiver implementations may realize varying values of t_clk-d, a transmitter must meet all related specifications for t_clk-d = N_d*T_bit, with N_d taking all integer values between 1 and N_ck-d+1.

10.3.4. Transmitter Deterministic Timing Error

The total deterministic (bounded) timing errors introduced by the TX shall not exceed 18% of a UI peak-to-peak. The evaluation of these timing errors must include all possible deterministic contributors, such as reference clock, clock distribution networks, duty cycle error (i.e., deviation from 50% duty cycle), skew between CLK and any D line, and power supply variation induced jitter or skew. Note that any such time-dependent error terms (i.e., jitter) that are correlated between the CLK and D lines must be filtered as described in Section 10.3.3.
This specification is a peak-to-peak requirement, so if a given design has e.g. +/-5% UI of duty cycle error, this would imply that it can achieve a TX deterministic timing error of no better than 10% UI.

10.3.5. Transmitter Total Timing Error

The total timing error introduced between the CLK and any data (D) line at the output of the TX shall not exceed 29% of a UI peak-to-peak at an error rate of 1e-15. The evaluation of errors must encompass all possible deterministic as well as random timing error contributors, including all sources of random jitter in addition to the representative deterministic error sources described in Section 10.3.4.

Assuming a Gaussian distribution for the random jitter, then in order to account for the 1e-15 error rate and peak-to-peak requirement, the total timing error t_err,tot may be computed as:

10.3.6. CLK Receiver Sensitivity to Common-Mode Variations

The differential receiver for the CLK signal within a BoW receiver must achieve an input-referred common-mode to differential conversion gain of less than 0.2 V / V. This requirement must be met across any common-mode input frequency less than or equal to 1/T_bit. For example, with a conformant BoW RX, 20mV of common-mode variation on the CLK+/CLK- lines must impact the effective differential input by less than 4mV.

Note that common-mode variations on the CLK+/CLK- lines of ~10-15% of the signal swing may be expected on typical in BoW channels.

10.3.7. Receiver Clock versus Data Path Delay

In order to be compatible with the TX jitter requirements provided in Section 10.3.3, for BoW-256 and low rate modes, a BoW receiver must capture data using clock edges that were launched by the TX no more than 3UI earlier than the data being captured. For BoW-384 receivers, data must be captured using clock edges that were launched by the TX no more than 5UI earlier than the data being captured. For BoW-512 receivers, data must be captured using clock edges that were launched by the TX no more than 6UI earlier than the data being captured.

10.3.8. Receiver Sensitivity and Timing Margin

A BoW receiver must meet a set of requirements on the following sets of timing and voltage error components:

• Maximum RX Deterministic Voltage Error: This term (V_err,det,RX) must include all deterministic voltage errors that would shift the receiver's voltage threshold relative to its ideal position in the middle of the signal swing. For example, any deterministic voltage errors due to residual offset, reference level error, and supply noise must be included. This specification accounts for the double-sided loss in margin, so if a given design has e.g. a residual threshold error of 0mV to +10mV, this would imply that the design can achieve a V_err,det,RX of no better than 20 mV.

• Maximum Total Required RX Voltage Margin: This term must include all possible voltage errors at the RX at a probability of 1e-15 or higher. In addition to the deterministic RX voltage error sources mentioned above, error sources such as receiver thermal/flicker noise must therefore be included in this term. For Gaussian random voltage noise, the total required voltage margin (V_err,tot,RX) may be computed as:

• Maximum RX Deterministic Timing Error: This term (t_err,det,RX) must include all deterministic timing errors that would shift the receiver's sampling timing relative to its ideal position for any data line. This term must therefore include errors due to e.g. residual sample timing position error, DLL dither, and power supply induced jitter. This specification accounts for the double-sided loss in margin, so if a given design has a mismatch-induced shift of the sampling position (relative to the ideal) of 0% to 5%, this would imply that the design can achieve a t_err,det,RX of no better than 10% UI.

• Maximum Total RX Timing Error: This term must include all possible timing errors at the RX at a probability of 1e-15 or higher. In addition to the deterministic RX timing error sources mention above, error sources such as RX clock receiver or clock distribution random jitter must be included in the total timing error. For Gaussian random jitter, the maximum total required timing error (t_err,tot,RX) may be computed as:

Since swing and signal integrity are expected to vary with termination as well as data-rate, the RX voltage and timing requirements are termination- and rate-dependent, as outlined in Table 14 and Table 15

10.3.9. Voltage Overshoot

This specification does not place a specific requirement on the overshoot observed by the RX, but it is expected that the overshoot should have magnitude of less than 300 mV for 750 mV I/O supply. Since overshoot is most likely to create potential reliability and other issues in unterminated operating modes, BoW RX's are allowed to turn on termination resistors to reduce the overshoot they observe. The value of the RX termination resistance in this case must be larger than 50 Ω, but is otherwise unconstrained as long as the receiver is able to meet its timing margin requirements with the resulting swing/channel.

BoW TX's therefore shall be designed to achieve their lifetime, reliability, and other requirements regardless of whether the BoW RX selects to operate with or without termination.

10.3.10. Slice-to-Clice CLK Skew

The slice to slice clock skew t_skew across the width of a BoW transmit link (along the chip edge) must be less than 150 ps/stack. (E.g., for a 4-stack interface, the skew from end to end must be less than 600 ps.) This skew includes only analog delays and specifically does not include any clock-related timing skew due to flip-flops/latches or varying reset states.

The slice to slice clock skew within a stack (orthogonal to the chip edge) for slices that are used within the same link must be less than 50ps/slice.

This skew is expected to be dominated by the TxClk distribution network.

11. Power Management

BoW PHYs may optionally implement the features/states described in this section in order to reduce average power consumption.

11.1. Data Idle State

The data idle state is defined by having the link layer set the value of all parallel data lines (including the optional AUX and FEC signals) fed into the PHY to logical 0 (0V at the output of the TX). In doubly terminated modes, a BoW PHY supporting this feature must connect the receiver's termination to 0V (ground). I.e., the selection of termination voltage is more restricted than as described in Section 9.

For the remainder of this section, a UI where all of the data lines are at logic 0 (0V) will be referred to as an “IDLE”. Note that real data with values of all 0's can still be transmitted/received by BoW PHY's supporting this feature.

11.2. Clock Gated State

While in the clock gated state, a BoW PHY TX ceases toggling the forwarded differential clocks CLK+/CLK-. In order to ensure proper operation of the PHY upon entry and exit from the clock gated state, a preamble and a postamble are appended to the payload data; these and further detailed requirements for entry, exit, and occupancy in this state are defined in the subsections below.

11.2.1. Signal Levels During Clock Gated State

During the clock gated state, a BoW PHY TX must drive differential low on the CLK+/CLK- signals. Similarly, while the PHY is in the clock gated state, the data signals must be IDLE (i.e., set to the data idle state).

Note that the use of static clock gated and data idle levels might result in aging of the TX/RX circuits within the PHY. PHY implementations may hence need to budget for the impact of this aging and/or include mechanisms to compensate for the errors introduced by such aging.

Note that the use of static clock gated and data idle levels might result in aging of the TX/RX circuits within the PHY. PHY implementations may hence need to budget for the impact of this aging and/or include mechanisms to compensate for the errors introduced by such aging.

11.2.2. Minimum Preamble, Postamble, and Payload Durations

In order to avoid the need to adjust the time alignment of parallel data words at the input/output of the PHYs due to entry/exit from the clock gated states, all durations of preamble, postamble, and payload must be set such that they are an integer multiple of the largest (between TX and RX) number of UI contained within a parallel input/output. For example, if a BoW TX with 4:1 serialization is communicating with a BoW RX using 8:1 deserialization, the preamble, postamble, and payload must all have durations of N_par*8 UI, where N is an integer greater than 1.

Since arbitrary serialization/deserialization ratios could result in very large minimum UI durations (due to the need to find the lowest common multiple), PHYs that support the clock gating mode must use only powers of 2 for the “Mux Ratio M” from Table 12.

BoW PHYs must publish as part of their datasheet the preamble, postamble, and payload lengths they support. It is strongly recommended that BoW interfaces support a configurable set of preamble, postamble, and payload length - particularly 4, 8, 16, and 32 UI.

11.2.3. PHY_Idle Timing and Parallel Data During Preamble / Postamble

As shown in Fig. 17, the PHY_Idle signal must be asserted (set to logic high) one TX parallel clock cycle earlier than the forwarded clocks enter the gated state. Similarly, the PHY_Idle signal must be deasserted (set to logic low) one TX parallel clock cycle earlier than the forwarded clock restarts.

The data driven into the PHY must be IDLE for all TX parallel clock cycles contained within the preamble, the postamble, or the clock gated states. Note that as shown in Fig. 18, if the pre or postamble lengths extend beyond a single TX parallel clock cycle, the pre/postamble duration must be extended by the link layer by padding the payload with additional IDLE data.

11.2.4. Maximum Duration of Occupancy Within Clock Gated State

To mitigate potential issues with drifts in various circuitry and/or control loops that depend on the clocks actively toggling (e.g., the receiver's DLL), BoW interfaces must not leave the forwarded clock gated for more than 1024 UI or 128 largest (between TX and RX) parallel words, whichever is smaller.

12. Chip-to-Chip Channel Specifications

BoW does not place any direct requirements on characteristics such as channel loss or crosstalk. Instead, BoW channels are considered conforming if they are able to achieve the required error rate of 1e-15 in conjunction with reference transmitters and receivers that meet all of the requirements provided in Section 9 and Section 10.3.

To assist with evaluating conformance of a given channel, open-source software evaluating signal integrity and the overall link budgets with the reference transmitters and receivers will be provided at a future date.

12.1. Channel-Induced CLK Edge to D Transition Skew at RX

Within each slice, a BoW channel should not introduce more than 2% UI of skew between any D lines and the CLK lines. For BoW-256, this corresponds to ~187.5 μm of length mismatch on a substrate with an ε_r of 4.

Note that the skew recommendation above is based on achieving sufficient timing margin on representative channels; channels with better signal integrity may allow for larger skew between the D and CLK lines as they meet the overall timing margin requirements.

Note further that if the BoW PHYs used on a given channel include per-bit delay adjustment, channels with larger skew can be supported. Note however that all of the timing requirements described in Section 10.3 must then be met with the residual skew and its variation over time taken into account.